Floating Point

Advanced Encryption Standard (AES) Cores

AES Product Brief (PDF)


Signali's family of Advanced Encryption Standard (AES) cores are FIPS-197 compliant, and designed to meet an application-appropriate balance between high throughput, low power, and minimal area in accordance with the product requirements and schedule. These cores are available for FPGA and ASIC designs.

  • Stand-alone AES 128-bit encryption with integrated on-the-fly key expansion
  • All standard modes of operation supported
  • A large variety of configurations, with optimizations in the areas of:
    • LUT/gate count
    • Block RAM usage
    • Latency
    • Data rate (bits/cycle)
    • Datapath width

AES is used to secure data-in-transit and data-at-rest for many common applications, including:

  • Wired and wireless communications: Secure Sockets Layer, Transport Layer Security
  • Encrypted storage: network-attached storage, storage-area network, iSCSI
  • Electronic financial transactions
  • Digital Rights Management
Example Configurations

Signali provides AES core implementations ranging from low resource utilization to extremely high frequency and throughput. Example performances and resource benchmarks are shown in the following table for the AES 128-bit core in ECB mode. All cores in the table have a datapath width of 128 bits, except for the AES_16 core, which has a datapath width of 16 bits.

IP Core Platform Resources Latency
LUTs Block RAM
AES Ultra Achronix Speedster 19,100 100 55 128 950 120
Xilinx Virtex-5 11,800 100 55 128 425 54
AES Std Xilinx Virtex-5 3,100 100 11 128 320 40
AES 16 Achronix Speedster 4,722 20 92 16 684 11
AES Tiny Xilinx Virtex-5 2,100 0 11 11.6 200 2

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